Lead Micro Architect and RTL Engineer (Architecture)
Qualification/Experience/Skills Required - Ability to define and describe (write specification for) system architecture, external interfaces, register definitions and operations, major partitions - Ability to write clear, concise documents and diagrams (timing, state machines, register maps, memory organization, synchronization sequences, etc.) to describe functional and operational (parametric) aspects of a complex SoC - Domain knowledge of various software applications and their underlying hardware requirements (e.g., networking, AI, Machine Learning, storage devices, IoT) - Experience in Digital module design and micro-architecture - Experienced at modeling complex state machines, datapaths and bus protocols/high speed (bandwidth) interfaces such as PCIe, USB, HBM, DDRx - Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics - Hands on in SoC level RTL integration - Hands-on expertise in writing System Verilog and VHDL - Hands-on in Perl/Tcl/Unix scripting - Excellent analytical, and problem solving skills - 15+ years' industry experience, Master's degree or equivalent in EE or Computer Engineering (CE) Roles & Responsibilities - Write clear, concise specification for an SoC including functional and timing descriptions for top level pins/ports/interfaces, registers and memories, state machines, datapaths, operating modes, exception/error handling, clocking, reset, power domains, etc. - Describe parametric/operating environment requirements including performance, power, area (PPA) targets, temperature and process ranges, IO pads, parametric tests, etc. - Interact with other system architects to define the application environment for the SoC being designed (firmware and OS requirements, external storage devices, sensor/analog components, etc.) - Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements - Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage - Technical interaction with engineering team